Tony,
Hi Larry
Your modern transputer sort of exists. Take a Raspberry-Pi 4 – it has 1 gigabit ethernet connection, 2 USB 3 and 2 USB 2 so using USB to ethernet dongles, you can effectively get up to 5 comms links, although their speed won’t be perfectly balanced, and you can use the wifi as the “control” port. People have built clusters of these for their own personal supercomputers.
The only problem here is the packet write latency, even over the
built-in ethernet it's likely to be several million cycles.I would
think very poorly of any solution that exceeded a thousand
cycles... especially as much of that delay is due to the I/O
blocks being "distant" (clock-wise) from the CPU core.
All we need is a kernel to support the comms and interpret the occam byte code – as it has a quad core processor, you could use one core to handle the comms, one the code interpreter and one the kernel.
@geerlingguy is one person who has blogged and youtube'd
extensively about this, and deserves a look if you're interested.
I would be very nervous about trying to create a new
architecture; people very commonly vastly underestimate the time
and effort taken for a new architecture to gain sufficient
traction to become useful. For ARM it was about a 15 years; ARC
never made it after over a decade trying; i960 tried for two
decades before dying; RISC-V is starting to make good progress
after a decade, buoyed by being open source and changing markets.
Starting from a known well supported base is far more likely to
produce a good result. If you're not keen on ARM, try RISC-V, as
it at least is open.
Regards,
Ruth
-- Software Manager & Engineer Tel: 01223 414180 Blog: http://www.ivimey.org/blog LinkedIn: http://uk.linkedin.com/in/ruthivimeycook/