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Not sure âtill I look at specs in more detail, but for my own usage I assume I will be just linking from my existing FPGA data capture to one of their channels.
: ââconsisting of source address, destination address, and dataâin a single clock cycle. Each routing link can transfer
up to 8 bytes of data on every clock cycle, allowing 64 bytes of data to flow through every routing node on every clock cycle, supporting an effective bandwidth of 64 GB/sec at a mesh operating frequency of 1GHz.â Beau From: Eric Verhulst (OLS) [mailto:eric.verhulst@xxxxxxxxxxxxxxxxxxxxxx]
This board looks cute and would be a nice target for us, but how to handle real-time I/O ?
Eric
From: Mailing List Robot [mailto:sympa@xxxxxxxxxx]
On Behalf Of J.B.W.Webber Like. I doubt if they will make their funding target, but I have put my $99 (actually $120 with international posting of the hardware) on the table. They put their main structural and programming document on the web a few days ago â just down loaded them â two IEEE FP operations and a 64bit load every cycle.
http://www.kickstarter.com/projects/adapteva/parallella-a-supercomputer-for-everyone/posts/323691
It would be very nice to have one of these hanging off to one side of my fast NMR data capture. Straight GCC, Eclipse, so I see no difficulty in porting code
using the aplc run-time library to each node. Just have to sort the aplc inter-chip communication. Ha. Wish I still had Helios. Cheers, Beau From: Mailing List Robot [mailto:sympa@xxxxxxxxxx]
On Behalf Of Barry Cook (4Links) Has anyone looked at this chip in any detail? Dr Barry M Cook CTO 4Links Limited, Suite EU2, Bletchley Park,
Sherwood Drive, Milton Keynes, MK3 6EB Tel: +44 1908 642001 Fax: +44 1908 363463 E-mail:
Barry@xxxxxxxxxxxx Web: www.4links.co.uk
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P
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