Re: Unclocked logic / delay insensitive circuits

[M_Boosten <mboosten@xxxxxxxxxxxxxxxxxxx>]

Hi Barry, Roger, and others...

> > Unclocked logic can easily be implemented in a CSP-based approach.)
> > 
> > Question: Barry, do you think you can implement it on an FPGA, or does
> >     that thing require the clock to be toggled regularly?
> >     (I would guess there is some kind of clocking requirement)
> 
> Yes.  You just ignore the clocked elements and use the combinatorial logic
> (with a little care to avoid glitches). It is rather a waste of the silicon
> area used for clocked latches - so it will be even more expensive to do
> unclocked than clocked until new devices are available :-(

Well, being able to implement it in an FPGA
gives confidence that a purpose-built IC will
work.

If it is a success, one could ask Altera, or some other
FPGA manufacturer to develop FPGAs optimized for
non-clocked systems...

What do you think?

	Marcel