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Re: Unclocked logic / delay insensitive circuits

M_Boosten wrote:
> Hi Barry, Roger, and others...
> > > Unclocked logic can easily be implemented in a CSP-based approach.)
> > >
> > > Question: Barry, do you think you can implement it on an FPGA, or does
> > >     that thing require the clock to be toggled regularly?
> > >     (I would guess there is some kind of clocking requirement)
> >

Asynchronous or self-timed logic has been modelled in CSP and
investigated in FPGAs since the earliest days. A fundamental element for
one style of self timed logic is a Muller C gate, and this was
implemented in the early Actel fuse FPGAs. It is too late tonight to
look out the references, but this stuff was covered extensively in the
early FPGA conferences, and as I noted elsewhere in the CSP community,
particularly with Mark Joseph's work with Tony Hoare. And one of the
motivations for my HCSP work was so that we could decouple an occam
program description of a circuit from the decision on whether to
implement it with synchronous or self-timed (asynchronous logic). Or
rather, to capture that in occam and make it compositional. That was one
of the ideas behind the SYNC constructor....

And we should note that Inmos looked into asynchronous logic many years
ago. Barry has mentioned some of the practical problems that have been

Dr A E Lawrence (from home)