Re: Unclocked logic / delay insensitive circuits

["B.M. Cook" <b.m.cook@xxxxxxxxxxxxxx>]

Marcel,

> If it is a success, one could ask Altera, or some other
> FPGA manufacturer to develop FPGAs optimized for
> non-clocked systems...
> 
> What do you think?

You will have to ask the manufacturer what "success" means. For a huge
investment programme they will need some convincing that there will be
enough sales.

You could ask Ian Page to comment (that's an invitation, Ian, having seen
that you read this group) on how hard it was to convince anyone to
manufacture his new FPGA design (based on content-addressable memory).

	  Barry.

-- 
/----------------------------------------------------------------------------\
| Barry M Cook, BSc, PhD, CEng, MBCS                                         |
| Senior Lecturer,                           Department of Computer Science, |
| Chartered Information Systems Engineer.    Keele University,               |
|                                            Keele,                          |
| Phone: +44 1782 583411                     Staffordshire,                  |
| FAX:   +44 1782 713082                     ST5 5BG,                        |
| email: barry@xxxxxxxxxxxxxx                UK.                             |
\----------------------------------------------------------------------------/