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RE: rewriting CSP processes

As I recall with the OS links, the reliability was calculated on the basis
of one latch sampling another. Each latch has a switching time i.e. a period
of metastability. These two cascaded i.e. the probability of one latch
sampling the other whilst it was in a metastable state gave the 1 part in
10e25 for the OS links. CERN spent years testing them before they had enough
proof that this was actually the case.

An interesting aside was that people used to call us up and complain that
the links only had a reliability of 1 part in 10e8 - the answer was always
that they had not followed the recommendations for track length and
specification for the PLL decoupling capacitor, and as a result, had noise
and jitter on the clock.

CERN have recently been doing similar work on the HS Links (IEEE1355), where
because of the much higher frequency, the metastability window is a greater
percentage of the bit rate (silicon speeds have not increased by as much as
the bit rate). For these links (1GHz), error detection circuits are

If anyone is interested, try looking at www.tachys.com

Tony Gore

email  tony@xxxxxxxxxxxx (alternative if problems tonygore@xxxxxxxxxxxxxx)
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-----Original Message-----
From: Stephen Maudsley [mailto:stephen.maudsley@xxxxxxxxx]
Sent: Friday, September 29, 2000 9:49 PM
To: Java-Threads Mailing List
Subject: Re: rewriting CSP processes

----- Original Message -----
From: "B.M. Cook" <b.m.cook@xxxxxxxxxxxxxx>
To: "Stephen Maudsley" <stephen.maudsley@xxxxxxxxx>
Cc: "Java-Threads Mailing List" <java-threads@xxxxxxxxx>
Sent: Friday, 29 September, 2000 3:24 AM
Subject: Re: rewriting CSP processes

> Stephen,
> > There's also a finite probability of simple logic levels being "wrong"
> > to noise margins etc.. in the semiconductors which practically sets an
> > end-stop on single device reliability. ISTR something of the order
> > for TTL but it's a while since I've worked with the numbers...........
> Thanks for this - I think I'd seen it before but wasn't really aware of
> I guess this is the probability of an input changing by enough to be at
> other logic level and staying there long enough for the gate to respond to
> it. Presumably the probability is rising with time, as noise margins drop
> and gates respond more quickly.
> Do you have any pointers to where the calculation is done?

ISTR statistical mechnics courses at university........

The issue came up when discussing the OS links over 10 years ago because the
figures were used for defining "good enough" for the oversamplers.... maybe
Paul Walker has a better recollection than me.

There were also related issues with the European Space Agency's work -
they've published a number of papers.

> A good place to find the metastability discussion and calculations is
> application notes on programmable logic, most now seem to have something,
> but the ones I first discovered were (I think) from AMD.

-- Stephen Maudsley, Esgem Limited mailto:Stephen.Maudsley@xxxxxxxxx
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