[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]

Re: rewriting CSP processes

----- Original Message -----
From: "B.M. Cook" <b.m.cook@xxxxxxxxxxxxxx>
To: "Stephen Maudsley" <stephen.maudsley@xxxxxxxxx>
Cc: "Java-Threads Mailing List" <java-threads@xxxxxxxxx>
Sent: Friday, 29 September, 2000 3:24 AM
Subject: Re: rewriting CSP processes

> Stephen,
> > There's also a finite probability of simple logic levels being "wrong"
> > to noise margins etc.. in the semiconductors which practically sets an
> > end-stop on single device reliability. ISTR something of the order
> > for TTL but it's a while since I've worked with the numbers...........
> Thanks for this - I think I'd seen it before but wasn't really aware of
> I guess this is the probability of an input changing by enough to be at
> other logic level and staying there long enough for the gate to respond to
> it. Presumably the probability is rising with time, as noise margins drop
> and gates respond more quickly.
> Do you have any pointers to where the calculation is done?

ISTR statistical mechnics courses at university........

The issue came up when discussing the OS links over 10 years ago because the
figures were used for defining "good enough" for the oversamplers.... maybe
Paul Walker has a better recollection than me.

There were also related issues with the European Space Agency's work -
they've published a number of papers.

> A good place to find the metastability discussion and calculations is
> application notes on programmable logic, most now seem to have something,
> but the ones I first discovered were (I think) from AMD.

-- Stephen Maudsley, Esgem Limited mailto:Stephen.Maudsley@xxxxxxxxx
-- http://www.esgem.com
-- Tel: +44-1453-521626 Mobile: +44-7770-810991
-- company registered in England 3372135, http://www.esgem.com/contact.htm