Re: rewriting CSP processes

["B.M. Cook" <b.m.cook@xxxxxxxxxxxxxx>]

Stephen,

> There's also a finite probability of simple logic levels being "wrong" due
> to noise margins etc.. in the semiconductors which practically sets an
> end-stop on single device reliability. ISTR something of the order 1:10^14
> for TTL but it's a while since I've worked with the numbers...........

Thanks for this - I think I'd seen it before but wasn't really aware of it.

I guess this is the probability of an input changing by enough to be at the
other logic level and staying there long enough for the gate to respond to
it. Presumably the probability is rising with time, as noise margins drop
and gates respond more quickly.

Do you have any pointers to where the calculation is done?

A good place to find the metastability discussion and calculations is
application notes on programmable logic, most now seem to have something,
but the ones I first discovered were (I think) from AMD.

	 Barry.

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| Barry M Cook, BSc, PhD, CEng, MBCS                                         |
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