# Re: rewriting CSP processes

```----- Original Message -----
From: "B.M. Cook" <b.m.cook@xxxxxxxxxxxxxx>
To: "Lawrence Dickson" <tjoccam@xxxxxxxxxxxxx>
Cc: "B.M. Cook" <b.m.cook@xxxxxxxxxxxxxx>; <IanPage99@xxxxxxx>;
Sent: Friday, 29 September, 2000 1:26 AM
Subject: Re: rewriting CSP processes

> Larry,
>
> >    In all this discussion of multiple clocks and
> > unclocked logic, I think this is the first mention
> > of metastability.
> >    That has always worried me, in all computer
> > smooth (time) function into a step function, and
> > deciding any race... Is it true there is always
> > a non-vanishing chance of failure?
>
> In a fully synchronous (i.e. all functions driven by the same clock
signal,
> and all logic delays small enough) system there is no problem.
>
> In an asynchronous system - very common - there is a metastability
problem.
> It is statistical and leads to a probability of failure. It is now well
> understood and we know what measurements to take to predict the
probability
> of failure. Some of the more recent chips have an inherently low failure
> probability. A widely used technique to re-synchronize signals is the
> multi-stage latch where each additional stage reduces the probability of
> error by about 4 orders of magnitude from the inherent already low
> probability. You can choose the number of stages to achieve your target
> error rate, in practice 2 stages is usually enough - that's just one extra
> latch per signal. The extra delay does add latency and hence reduces
> throughput. There is no problem letting a synthesis tool put the logic in
> for you.
>
> Yes, it is true that there is always a non-vanishing chance of failure,
but
> it can be made as small as you like.
There's also a finite probability of simple logic levels being "wrong" due
to noise margins etc.. in the semiconductors which practically sets an
end-stop on single device reliability. ISTR something of the order 1:10^14
for TTL but it's a while since I've worked with the numbers...........

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