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XCore matters

All,

I am attempting a branching off here. I realise I may be the only interested person. 

But then I feel that some XCore matters convey relevant points as per the rest of the theme(s) of this thread (else they might not have been put on the table). 

And besides, we have the designer available:

David (cc all),

6. des. 2020 kl. 19:17 skrev David May <David.May@xxxxxxxxxxxxx>:

...

It is entirely possible to fix the problems with communication set-up and completion - one option is the microprogrammed transputer-style implementation;
.
another is the multithreaded XCore style with single-cycle i/o instructions (which means that threads can act as programmable DMA controllers);

Is it possible that you could explain this?

Is the "programmable DMA controller" something explicit in XC or is it implicit for (not really?) any communication between cores on tiles or between tiles or ports. Or is it the channels or interfaces, or use of (safe) pointers?

- - -

Even if now have programmed in XC for years I can ask such s.. questions! 

Here are some points I found by searching for «DMA» in the folder I have where I keep loads of downloads of XMOS/XCore related documents:

In [1] chapter 1.6 The underlying hardware model, it says (page 15/108) that:

* The memory on each tile has no cache.
* The memory on each tile has no data bus contention (all peripherals are implemented via the I/O sub-system which does not use the memory bus; there is no DMA for peripherals).

The last two properties ensure that a load or store from memory always takes one or two instruction cycles on each core. This makes worst case execution time analysis very accurate for code that accesses memory.

Tasks on different tiles do not share memory but can communicate via inter-core communication.

In xC, the underlying hardware platform being targeted provides a set of names that can be used to refer to tiles in the system. These are declared in the platform.h header file. The standard is to provide an array named tile. So the tiles of the system can be referred to as tile[0], tile[1], etc.

In [2] you write that (‘Threads’ page 7, also mentioned in XARCH2010 paper)

Threads are used for latency hiding or to implement ‘hardware’ functions such as DMA controllers and specialised interfaces

In [3] you write that (‘Processes - use ’ page 12, also in NOCS paper)

Implement ‘hardware’ functions such as DMA controllers and specialised interfaces

In [4] «DMA» is only used in the context of communication with the (odd!) ARM core on the dice. Like through library calls as «xab_init_dma_write». 



Øyvind

PS. For later I also have some other XCore themes to attempt asking..