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RE: rewriting CSP processes
> -----Original Message-----
> From: B.M. Cook [mailto:b.m.cook@xxxxxxxxxxxxxx]
> Sent: 02 October 2000 12:22
> To: tjoccam@xxxxxxxxxxxxx
> Cc: b.m.cook@xxxxxxxxxxxxxx; IanPage99@xxxxxxx;
> occam-com@xxxxxxxxx; ian.page@xxxxxxxxxxxx
> Subject: Re: rewriting CSP processes
> Larry, Stephen, and everyone else ...
> > In all this discussion of multiple clocks and
> > unclocked logic, I think this is the first mention
> > of metastability.
> The book I mentioned before has more information than I remembered:
> "Introduction to VLSI Systems" by Carver Mead & Lynn Conway
> (A classic book
> on VLSI design) from ~1980.
> In particular,
> Chapter 7, "System Timing" (written by Charles L Seitz) details the
> metastability issues and describes, with examples, self-timed systems.
ALTERA provide an application note on metastability (No 42), which can be
obtained from their web site. This note explains the formulae for
calculating the Mean Time Between Failure (MTBF) for a device and provides
the data for calculations with several of their devices. Also it worth
stating that in circuit where a metastable state can occur it is not
possible to transfer data on every cycle of the clock.
> Chapter 9, "Physics of Computational Systems" includes the
> limit Stephen
> reminded us of.
Could someone explain the term ISTR used by Stephen.
Brian C. O'Neill | Tel: +44 0115 848 6044
Dept of Elec & Electronic Eng | Fax: +44 0115 848 6567
Nottingham Trent University | E-mail: Brian.ONeill@xxxxxxxxx
Nottingham | http://eee.ntu.ac.uk/research/parallel
NG1 4BU |