Re: Unclocked logic / delay insensitive circuits

[M_Boosten <mboosten@xxxxxxxxxxxxxxxxxxx>]

Hi,

Barry:
> My view - Yes, indeed it is an extremely good match.

(Barry's conclusion:
Unclocked logic can easily be implemented in a CSP-based approach.)

Question: Barry, do you think you can implement it on an FPGA, or does
    that thing require the clock to be toggled regularly?
    (I would guess there is some kind of clocking requirement)
    
    In case it does, cannot you toggle it at some low frequency, and not
    be bothered with the frequency in the implementation.
    (I would guess this is practically impossible for some simple reason)
    
What do you think?
	Marcel