Re: Unclocked logic / delay insensitive circuits

["B.M. Cook" <b.m.cook@xxxxxxxxxxxxxx>]

Marcel,

> CSP is very succesful in compilation to clocked logic.
> What about compilation to unclocked logic?

No problem at all. It is built-in to such logic that an indication of
completion/data-is-ready moves with the data. The event(/channel) idea is
already present.

[For a nice introduction to this, see Mead & Conway's (~1975) book on VLSI
design. There is a chapter near the end with references to the foundation
work.]

> I know Philips research has been performing significant
> research in this area: they call it delay insensitive
> circuits.

Also Steve Furber's work at Manchester University which includes a very
successful implementation of an ARM core - the AMULET.

Advantages you list PLUS much reduced electrical emissions since the edges
are not synchronised there is no fundamental frequency that everything
contributes to.

Unfortunate disadvantage is that it uses more silicon area than clocked
logic so it isn't always the implementation of choice :-(

> Question:
>    Cannot dealy insensitive circuits be simply implemented with a
>    CSP-based approach?
>    
> My impression:
>    It should be.

My view - Yes, indeed it is an extremely good match.

          Barry.

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| Barry M Cook, BSc, PhD, CEng, MBCS                                         |
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