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Re: rewriting CSP processes


> > Clocked logic only changes state on clock edges, it is not possible to
> > distinguish time intervals less than a clock cycle time. ...
> >  With real delays from propagating signals we increase the
> > clock period (slow the system down) until the above holds. 
> > 
> 	But there is a price for such convenience...the performance of
> 	the whole system is at the mercy of the longest logic chain.

This is true, but also not necessary.

Sometimes it is convenient to implement big logic chains and some tools do
so (e.g. Handel-C) - but it isn't necessary. I am building a research
compiler that produces no more than a single layer of logic - the downside
is that timing is more hidden and a proper means to specify time will need
to be added. For results on a prototype compiler which is mid-way between
unconstrained levels of logic and the new target, see papers by myself and
Roger Peel at PDPTA and CPA-2000 (Dyke will have a copy of these).

> > It is *very* much harder to synchronize logic with multiple clocks and
> > other
> > realities.
> > 
> 	Shouldn't it be possible to automatically deal with such issues?

Yes. My new compiler will handle multiple (unsynchronized) clocks and do
this for you; but the resulting logic is somewhat more complex than the
single-clock case and bandwidth between clock domains is more limited than
within a domain.


| Barry M Cook, BSc, PhD, CEng, MBCS                                         |
| Senior Lecturer,                           Department of Computer Science, |
| Chartered Information Systems Engineer.    Keele University,               |
|                                            Keele,                          |
| Phone: +44 1782 583411                     Staffordshire,                  |
| FAX:   +44 1782 713082                     ST5 5BG,                        |
| email: barry@xxxxxxxxxxxxxx                UK.                             |