On Jun 20, 2013, at 10:08 AM, Ruth Ivimey-Cook <ruth@xxxxxxxxxx> wrote:
Larry Dickson wrote:
If it were me I'd need an generalised and fast interconnect that was at least as good as the old Tp virtual router, then make I/O connections (A-D, etc) dedicated entities in preference to having "special" CPUs... that always causes problems in implementation.
We seem to be talking past each other here. The virtual router (if it's the crossbar switch I'm thinking of) connected multiple Transputers (separate chips) where I believe Prof. May is talking about thousands of Transputers on a single die. You could add a crossbar switch (or a bunch of them) within the die but the question would still remain which of the Transputers each crossbar was connected to. Basically, programming the crossbars would replace programming the "edge" Transputers, and that looks even more complex to me, two species to deal with, and a lot of virtualization, which could be either a plus or a minus. As I remember, non-default settings of the crossbars were little used on the historic Transputer boards.
I don't see why. There could be a general address space (probably 2D) and each Transputer would have its home region in that space, closely resembling its actual location on the die. Then just allow 2D <-> 1D memory aliasing primitives (subarray - stride) and everything stays natural instead of the horrible distortions introduced by VM.
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Larry says : “I don't see why. There could be a general address space (probably 2D) and each Transputer would have its home region in that space, closely resembling its actual location on the die. Then just allow 2D <-> 1D memory aliasing primitives (subarray - stride)”
This is somewhat similar to the memory on the Adapteva Epiphany : each processor can address the whole memory set using a 32 bit address, it is just faster to access the local memory using a part of the address range.