RE: Massively parallel FPGA systems

["Stephen Maudsley" <Stephen.Maudsley@xxxxxxxxxxxxxxxxxxxxxx>]

I worked on several machines in the 80's and 90's where we wrapped a shared
bus in a message passing arbitration scheme (some used links). These were
for signal processing applications where we had high bandwidth single point
data sources. Most of them were quite regular data structures close to a
sensor but we also had a couple of machines where the raw data had been
pre-processed so that you could consider it an object stream with objects
ranging in size from 64 bits to 64kbits (probably closer to a CPU data bus)
and the design scheme still worked. I suspect some of the postal sorters are
still using that architecture in the back-end of the recogniser.

-----Original Message-----
From: Roger Peel [mailto:R.Peel@xxxxxxxxxxxxxxxx]
Sent: 13 October 2003 19:06
To: Lawrence Dickson
Cc: occam-com@xxxxxxxxxx
Subject: Re: Massively parallel FPGA systems


>
> Now that Starbridge has been panned -
>
> Does anybody out there know any massively parallel single-die chips
> made of huge numbers of identical little CPUs? In reality, in
> vaporware, in patents, or a glimmer in someone's eye... I don't
> mean any wimpy 64, I mean thousands. Starting from the fact that
> newest Pentium has over 100 million transistors, and a perfectly
> good CPU of the 1980s can be made with 40,000.
>
> They are interested at work, so please send any Windows-style
> attachments to my work address (ldickson@xxxxxxxxxxx) as this
> ancient ISP can't deal with them.
>
> Larry Dickson

Larry,

Back in 1998, the Electronic Frontier Foundation built a multi-FPGA
machine capable of cracking Data Encryption Standard keys (See
http://www.eff.org/descracker/).  This machine ran 64 cracking
processes per FPGA - although whether these qualified as "little CPUs"
is debatable.  (see http://www.itsecurity.com/papers/crackdes6.htm)

Using current FPGA technology, thousands of processes per chip should
be possible.

I'm still working on a compiler that takes Occam/CSP and targets FPGAs,
with the specification and implementation of transputer-like CPUs as
one major goal, so I would be interested in your applications of a
multi-processor FPGA.  Interestingly, the internals of a CPU appear
quite difficult to specify efficiently in a CSP-like language, and also
quite difficult to implement in FPGA [think "shared data bus" in both
cases].

Roger.