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RE: Priority revisited: a new primitive


Your example is in the spirit of my example. The PRI ALT in your example
nicely terminates when the PAR terminates. This is something I have
overlooked. The example I showed was focused on communication and your
example is more general. The reason I used channel events was that this
could be implemented in Occam or with one of the CSP for Java libraries
(e.g., JCSP or CTJ).


-----Original Message-----
From: ael@xxxxxxxxxxxxxxxxxx [mailto:ael@xxxxxxxxxxxxxxxxxx]On Behalf Of
A E Lawrence
Sent: woensdag 11 oktober 2000 4:56
To: g.h.hilderink@xxxxxxxxxxxxx
Cc: Occam-com mail group
Subject: Re: Priority revisited: a new primitive

I confess that I got a bit lost in Gerald's implementations, but if I
give a algebraic semantics - an example anyway - perhaps it will help.

Using pseudo-occam,

PAR PRI [{a}]

is equivalent to (=)

    sampling := TRUE
    WHILE sampling
            sampling := FALSE

The equivalence is only true if a is an event in the alphabet of
PAR [P1,P2,...,Pn].

Sorry, that really needs folding, but still. In real occam, "done" will
be a channel which may be written by the second component to signal that
it has terminated.

"a" is a high priority event, and in the CSP intended above would be a
three-way synchronization if it represented an external channel
communicating with one or more of the Pi processes. In occam, any
instance of that event would be with just one of the Pi, of course. It
is still a three-way synchronisation when a represents internal
communication between or within any of the Pi. I do not exclude the case
where the event a represents an assignment, but I am not sure whether
that would be useful.

The three way synchronization means that this isn't a direct occam
implementation: it should be trivial to convert it, but surely that
would only obscure the semantics?

I think that this equivalence is in the spirit of Gerald's examples?
I will post a couple of more complex examples later.

The operational semantics is simpler, I think. The idea is that there be
a dedicated scheduling mechanism to handle this as efficiently as
possible on whatever target is involved, hardware or software.

Dr A E Lawrence