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Is PRI PAR useful for hardware?

Is PRI PAR useful for hardware?

We usually think of PRI PAR as a mechanism for managing a limited software 
resource - mainly time - on a uniprocessor.

But resources are also limited in hardware. In reconfigurable technology,
the limited resource is usually space. With partially reconfigurable
hardware like the late lamented XC6000 series, the whole point is to
dynamically reload sections of a chip with the most urgent task: exactly
the function of PRI PAR?

This is really thinking out load following comments at WoTUG-22, especially
by Barry, to the effect that perhaps PRI PAR is not needed.
But I don't undrstand the alternative proposal: was it based on the idea
that priority is attached to events rather than processes? I am not really
sure that CSPP does not already attach priority to events.


A E Lawrence, MA., DPhil.  	adrian.lawrence@xxxxxxxxxxxxxx
MicroProcessor Unit, 13, Banbury Road, Oxford. OX2 6NN. UK.                
Voice: (+44)-1865-273274,  Fax: (+44)-1865-273275