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Re: (fwd) T9000 News (fwd)

Yes I would be very interested in such a device.

Also enclosed at the bottom is the copy of a interchange between myself 
and Tony Gore (ex-Inmos) which details further my interest


On Tue, 10 Dec 1996, Ian Page wrote:

> We are actively considering getting into a project to put DS links and VCP
> onto FPGA technology so that they could easily be integrated with other
> host processors. If it comes off, we would describe the system in our 
> Handel-C language and compile onto the FPGAs so that it would be relatively
> easy to parametrise the design and also to map to different FPGAs.
> Other implementations such as ASIC ones are also possible (though with
> significantly higher NRE costs).
> It would be interesting for us to know what support there might be for a 
> project like this from the (disenfranchised) transputer converts. In
> particular, is it (a) a silly idea, (b) a good idea, (c) a good idea
> with an identifiable market that will make the effort of doing the work 
> worthwhile?
> Cheers,
> Ian
> See http://www.comlab.ox.ac.uk/oucl/hwcomp.html for further details on
> our work (though not on the VCP project).

Mail interchange with Tony Gore

There is an FPGA implementation of DS links done by Keele University and
Paul Walker (4 Links, Milton Keynes).

Also, there is an OMI proposal about to be submitted that will do a VCP
implementation in FPGA.

I think that there is a whole community that has been waiting and will be
galvanised into action now that ST has made its decision. There is going to
be some very interesting legal issues. Why?

Well ST did the VCP as part of the ESPRIT PUMA project, and under ESPRIT
contractual rules, any European company can go to the EC and demand that the
IP be released if it is not being, or planning to be, exploited by ST. It is
the downside for having public money.     

As an inexpert on IPR (I have a certain amount of responsibility) and
knowing the history of more of this from the other side, I am longing to see
some of these contractual clauses put into practice. For far too long, the
big companies have been scamming EC money and putting nothing back (that was
why I had been looking for an out from ST for several years).

With the DS links available for low cost licensing ($5k approx is a
prequisite for IEEE as in IEEE 1355), even some of the background is
available. Also, within OMI, DASA have designed and built chips for using DS
links to build parallel processors based on AMD DSPs. It may be just what
you want. Look at www.omimo.be - try press and the products sections.

I will present something tomorrow to the OMI Advisory Group that basically
says that once we get down below 0.2 micron or so, off chip buses cannot be
single cycle and synchronous, unless pipelined, and even the I/O on a chip
will not all go on the bus - reason - propogation delays will go from 1ns/cm
to 6ns/cm - this means at 200MHz, which will no longer be leading edge, the
clock will be 180 deg out of phase in 4mm. Thus, high speed serial (i.e.
David May's narrow links) will replace many buses (David May's fat links).

We are fast approaching the time when CSP will be essential for chip

Must go - got a proposal in which Aspen Enterprises Limited (my company)
has to complete before deadline (OMIMO only employs me 75%). 


From:  jmk 
To:  Tony Gore Subject:  
Re:  Contact 
Date:  Wednesday, December 11, 1996 17:28


My interest in OMI is tenouos but I am currently doing what I have wanted
to do for a long time, namely connect a disc EIDE directly to a DS-link
so that we can use the small format DS-link connector, rather than a
40-pin connector!!.

We can then use a C104 as a large switch between a processor and the
discs.  I would quite like to put an FPGA between the C104 and the disc
so that we can pre-process data coming from the disc.

The nature of the processor is quite interesting given that the T9 is on
the way out !!  will there be a processor with VCP and DS-links?


Professor JM Kerridge		tel   	+(0) 131 455 4395
Department of Computer Studies	fax 	+(0) 131 455 4552
Napier University			email 	j.kerridge@xxxxxxxxxxxxxxxx
219 Colinton Road
EH14 1DJ