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Re: rewriting CSP processes

"B.M. Cook" wrote:
> John, et al.
> > I've a CSP question. The words around the mathematics
> > talk about "events" being instantaneous transactions that
> > are handshaken (both the Roscoe and Schneider books
> > use those terms).  In real life, that's not possible.  Handshaking
> > protocols don't execute in zero time, and signals don't
> > propagate instantly.  Is there anything in the CSP literature
> > that deals with this problem?
> >...
> There are some (common) situations in which things appear as required.
> Clocked logic only changes state on clock edges, it is not possible to
> distinguish time intervals less than a clock cycle time. Here it is easy for
> each synchronizing process to assert a signal to indicate its readiness, and
> for a logical AND of all the participants to indicate (in the clock cycle
> that it happens) completion. *Effectively* we have "instantaneous"
> transactions. With real delays from propagating signals we increase the
> clock period (slow the system down) until the above holds. (Aside, the
> maximum clock rate for things like processors is determined by propagation
> delays across the silicon. A proposed solution is to divide the chip into
> local clock domains with message passing between them - and the world
> re-invents transputers!)
> It is *very* much harder to synchronize logic with multiple clocks and other
> realities.
> There is also Adrian's timed CSP.

Yes, but for this sort of situation, we only need discrete events and
the standard traces model if you use my "merge" algebra: you can have
your cake and eat it :-)

The model avoids "true concurrency": only one event can happen at once.
But if that event is a "merged" event of, say, a clock edge with 1000
processes representing 1000 clbs in an FPGA, then in effect you have
1001 truely simultaneous events. All this is in the original HCSP ,is
one way of viewing

x,y := a,b

in occam, and is in Barry's hardware compiler as SYNC among other
At one time, a restricted version was called MAS, but I'm not sure
whether the early discussions that Barry and I had about that went

Note of course that these are abstractions. The hardware implementations
of the above probably do qualify as really concurrent. But a software
implementation of the multiple assignment is likely to be an abstraction
which hides the several, probably sequential, underlying events. Hiding
and abstraction are crucial and fundamental aspects of CSP and are
easily overlooked if you are primarily concerned with programming in
occam. Of course it is there, partially in scope rules, but it is not so
obvious unless you have the CSP framework as a reference.

Dr A E Lawrence