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"O'Neill, Brian" wrote:
> Larry wrote
> > Barry and all,
> > In all this discussion of multiple clocks and
> > unclocked logic, I think this is the first mention
> > of metastability.
> > That has always worried me, in all computer
> > design including occam and CSP. Transforming a
> > smooth (time) function into a step function, and
> > deciding any race... Is it true there is always
> > a non-vanishing chance of failure?
> > Larry
> I have worked with asynchronous circuit for many years and operated them in
> a mode where there is a high probability of repeated occurrence of a
> metastable state. The most important issue is how the circuit recovers from
> a metastable state. With modern ASIC and FPGA devices this is usually not a
> problem. ALTERA FPGAs will recover from a metastable state within 2ns. I
> have run tests for many hours of continuous operation without error which
> would indicate that the above figure is correct.
> Unfortunately you cannot state that there will never be a failure due to
> metastability only that the probability is very small and less then other
> modes of failure.
And I should add that Mark Josephs worked with Tony Hoare a number of
years ago on modelling asynchronous circuits using CSP. IIRC the events
were transitions. And I did a fair bit of work on the early Handel
compilers in implementing metastability guard circuits.
Dr A E Lawrence (from home)