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Dynamic Priority



Well I am still throwing ideas into the pond to see if they can swim. It
will be obvious to you all that they  are not even half baked. But I
hope that some consensus about one or more useful primitives may emerge.

I am confident about the future of occam especially in co-design. But
identifying the right notions has much wider applicability. 

While I agree that we need a way of specifying requirements perhaps
using SATISFYING (which I now think can be a qualifier on almost any
line of occam)[1] we also have the heritage of PRI PAR. And theer are
occasions when we want explicit control, at least I do. It might even be
useful in building the compiler implementations: that too needs to be
something we can formalize.

So here goes. Expanding on URGENT events, it seems easy to give a
semantics to 

CHAN OF URGENT type name:
PAR
  P0
  P1
  ...
which seems to capture the "priority on events", and I think matches
what Gerald and the Twente team have done in CTJ.

Well, I suppose it has to allow an order among several URGENT channels:-

CHAN OF URGENT[2] type_2 priority2:
CHAN OF URGENT[1] type_1 priority1:
PAR
  ...

This gets awkward with CHAN arrays. Maybe a replicator sort of syntax:
[i]CHAN OR URGENT[table[i]] type priority i = 0 FOR n :
No, I don't like it either.

PAR
  URGENT
    CHAN OF a1 b1:
    CHAN OF a2 b2:
  P0
  P1
  ...

I don't think the guard-like syntax has to suggest a process? Still
syntax is
secondary. 

I guess that we now have to add dynamic priority so the PAR can take a
priority/order channel: PAR(CHAN OF stuff priority)...

Once more, I think it straightforward to give a CSPP acceptance
semantics
to this sort of thing. Else I wouldn't have made the suggestion.:-) .
Seriously, it is having this proper foundation that gives me the
confidence to play with these ideas and think about them clearly. Eh,
sometimes..  

Adrian

-------------------------------------------------------------------------
[1] SATIFYING/SATIFIES is a good way to express hardware constraints
like set-up-and-hold margins, propagation delays and the like... VHDL
watch out!

-- 
A E Lawrence, MA., DPhil.  	adrian.lawrence@xxxxxxxxxxxxxx
MicroProcessor Unit, 13, Banbury Road, Oxford. OX2 6NN. UK.                
Voice: (+44)-1865-273274,  Fax: (+44)-1865-273275