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Anyone noticed that the next generation of Alpha will support
'multi-threading'? (http://www.theregister.co.uk) Together with packet
based RAMBUS RAM, perhaps we will get a ParaPC of sorts after all... I
still don't understand why Intel took the approach that it has in hiding
memory latency in the Merced, when hardware context switching provides a
much more scalable alternative.
Jim Moores, PhD Research Student, Computing Lab, University of Kent, UK.
new email address: jimmoores@xxxxxxxxxxx